1. Field of the Invention
The present invention relates to methods for embedding and/or de-embedding networks when, for example, making measurements using a vector network analyzer (VNA). More particularly, the present invention relates to calculations for embedding and/or de-embedding networks that are not directly amenable to chain matrix calculations, such as three-port devices and semi-balanced devices with an odd number of ports.
2. Description of the Related Art
Measurements of a device under test (DUT) using a VNA may not always be performed in a desired test environment. This is because it maybe too time intensive and/or costly to measure a DUT in a desired test environment. Accordingly, a DUT is often measured in a different environment for reasons of expediency and/or practicality, thereby requiring the use of embedding or de-embedding techniques to correct the effects of the test environment. For example, a DUT may be in a test fixture or connected via wafer probes when measurements of the DUT are made, thereby requiring the removal of the effects of the fixture or probes from the measured data for a truer picture of actual DUT performance. De-embedding techniques allows this task (i.e., removal of effects) to be performed computationally. This concept is shown in FIG. 1A. In another example, a customer may desire to see what the performance of a DUT would be with a specific matching network attached. However it may be impractical to attach the matching network during manufacturing for cost reasons. Embedding techniques allow this task (i.e., attaching the matching network) to be performed computationally. This concept is shown in FIG. 1B.
While most commercial simulators use nodal wave analysis or similar techniques for computing composite network results, these approaches may not be needed or wanted (e.g., based on computational or memory needs) for certain specific applications. Among these applications are embedding or de-embedding networks to/from a measurement. For two port devices, a chain matrix or cascading computation using transfer-matrices has been used to perform embedding and de-embedding. The concept is to re-arrange standard scattering-parameters (S-parameters) to form a pair of new matrices (termed T for transfer matrices) that can be multiplied for embedding and form the equivalent to the networks being concatenated or cascaded (i.e., one network being embedded). Multiplying by the inverse of the T-matrix (i.e., Txe2x88x921) is the equivalent of de-embedding. A key-point is that the outputs from one stage map directly to the inputs of the next stage thereby allowing the matrix multiplication to make sense.
Transfer-matrices (also known to as transmission matrices) are made up of T-parameters (also known as chain-scattering-parameters and scattering-transfer-parameters) that are defined in a manner analogous to S-parameters except the dependencies have been switched to enable the cascading discussed above. In both cases the wave variables are defined as ai for the wave incident on port i, and bi for the wave returning from port i. S-parameters of an n-port device characterize how the device interacts with signals presented to the various ports of the device. An exemplary S-parameter is xe2x80x9cS12xe2x80x9d. The first subscript number is the port that the signal is leaving, while the second is the port that the signal is being injected into. S12, therefore, is the signal leaving port 1 relative to the signal being injected into port 2. Referring to FIG. 2, the incident and returning waves and the S-parameters are shown for an exemplary two-port network 202. These S-parameters are defined by Equation 1 below.                               [                                                                      b                  1                                                                                                      b                  2                                                              ]                =                              [                                                                                S                    11                                                                                        S                    12                                                                                                                    S                    21                                                                                        S                    22                                                                        ]                    ⁡                      [                                                                                a                    1                                                                                                                    a                    2                                                                        ]                                              (                  Equation          ⁢                      xe2x80x83                    ⁢          1                )            
where,
a1 is the traveling wave incident on port 1;
a2 is the traveling wave incident on port 2;
b1 is the traveling wave reflected from port 1;
b2 is the traveling wave reflected from port 2;
S11 is referred to as the xe2x80x9cforward reflectionxe2x80x9d coefficient, which is the signal leaving port 1 relative to the signal being injected into port 1;
S21 is referred to as the xe2x80x9cforward transmissionxe2x80x9d coefficient, which is the signal leaving port 2 relative to the signal being injected into port 1;
S22 is referred to as the xe2x80x9creverse reflectionxe2x80x9d coefficient, which is the signal leaving port 2 relative to the signal being injected into port 2; and
S12 is referred to as the xe2x80x9creverse transmissionxe2x80x9d coefficient, which is the signal leaving port 1 relative to the signal being injected into port 2.
(Note that the set of S-parameters S11, S12, S21, S22 make up an S-matrix)
The T-formulation is a bit different to allow for cascading. More specifically, in the T-formulation, b2 and a2 are independent parameters rather than a1 and a2 (as in the S-formulation of Equation 1). This does not change the operation of the circuit, just the situation under which the parameters are measured. Since T-parameters are rarely measured directly, this is usually not a concern. For a two-port network, the T-parameters are defined in Equation 2 shown below.                               [                                                                      a                  1                                                                                                      b                  1                                                              ]                =                              [                                                                                T                    11                                                                                        T                    12                                                                                                                    T                    21                                                                                        T                    22                                                                        ]                    ⁡                      [                                                                                b                    2                                                                                                                    a                    2                                                                        ]                                              (                  Equation          ⁢                      xe2x80x83                    ⁢          2                )            
Two cascaded two-port networks 302 and 304 are shown in FIG. 3. Note the arrangement is such that when two networks are connected together, b2 of network 302 at the left maps directly onto a1 for network 304 on the right. Similarly, a2 for network 302 on the left maps directly onto b1 for network 304 on the right.
The equations for computing the T-parameters in terms of the S-parameters (and vice versa) can be mathematically derived. The results are shown below in Equations 3 and 4.                               [                                                                      T                  11                                                                              T                  12                                                                                                      T                  21                                                                              T                  22                                                              ]                =                              1                          S              21                                ⁡                      [                                                            1                                                                      -                                          S                      22                                                                                                                                        S                    11                                                                                                                                      S                        21                                            ⁢                                              S                        12                                                              -                                                                  S                        11                                            ⁢                                              S                        22                                                                                                                  ]                                              (                  Equation          ⁢                      xe2x80x83                    ⁢          3                )                                          [                                                                      S                  11                                                                              S                  12                                                                                                      S                  21                                                                              S                  22                                                              ]                =                              1                          T              11                                ⁡                      [                                                                                T                    21                                                                                                                                      T                        11                                            ⁢                                              T                        22                                                              -                                                                  T                        21                                            ⁢                                              T                        12                                                                                                                                          1                                                                      -                                          T                      12                                                                                            ]                                              (                  Equation          ⁢                      xe2x80x83                    ⁢          4                )            
The above analysis and equations are useful for embedding and/or de-embedding two-port networks. A concept for embedding and/or de-embedding four-port networks is disclosed in commonly invented and assigned U.S. patent application Ser. No. 10/050,283, entitled xe2x80x9cMethods for Embedding and De-Embedding Balanced Networks,xe2x80x9d filed Jan. 15, 2002, which in incorporated herein by reference in its entirety. FIG. 4 illustrates such a four-port network 402 in which ports 1 and 2 are treated as a first pair of ports (with waves a1, b1, a2 and b2 being referred to as first pair waves), and ports 3 and 4 will be treated as a second pair of ports (with waves a3, b3, a4 and b4 being referred to as second pair waves). The S-parameters associated with four-port network 402 of FIG. 4 are defined by Equation 5A, shown below. To enable cascading, the waves associated with ports 3 and 4 (i.e., a3, b3, a4 and b4) are treated as independent variables of a T-matrix equation, and those associated with ports 1 and 2 (i.e., a1, b1, a2, b2) are treated as dependent variables. This leads to the T-matrix shown in Equation 5B below.                                                                         [                                                                                                    b                        1                                                                                                                                                                                                                                    b                              2                                                                                                                                                                                          b                              3                                                                                                                                                                                          b                              4                                                                                                                                                                          ]                            =                                                [                                                                                                              S                          11                                                                                                                                                                                                                S                                12                                                                                                                                                    S                                13                                                                                                                                                    S                                14                                                                                                                                                                                                                                                                                                                                            S                                21                                                                                                                                                                                                        S                                31                                                                                                                                                                                                        S                                41                                                                                                                                                                                                                                                                                                    S                                22                                                                                                                                                    S                                23                                                                                                                                                    S                                24                                                                                                                                                                                                        S                                32                                                                                                                                                    S                                33                                                                                                                                                    S                                34                                                                                                                                                                                                        S                                42                                                                                                                                                    S                                43                                                                                                                                                    S                                44                                                                                                                                                                                          ]                                ⁡                                  [                                                                                                              a                          1                                                                                                                                                                                                                                                        a                                2                                                                                                                                                                                                        a                                3                                                                                                                                                                                                        a                                4                                                                                                                                                                                          ]                                                                                        xe2x80x83                                                          (                  Equation          ⁢                      xe2x80x83                    ⁢          5          ⁢          A                )                                          [                                                                      a                  1                                                                                                                                                                        a                        2                                                                                                                                                b                        1                                                                                                                                                b                        2                                                                                                                          ]                =                              [                                                                                T                    11                                                                                                                                                                T                          12                                                                                                                      T                          13                                                                                                                      T                          14                                                                                                                                                                                                                                                              T                          21                                                                                                                                                              T                          31                                                                                                                                                              T                          41                                                                                                                                                                                                                                  T                          22                                                                                                                      T                          23                                                                                                                      T                          24                                                                                                                                                              T                          32                                                                                                                      T                          33                                                                                                                      T                          34                                                                                                                                                              T                          42                                                                                                                      T                          43                                                                                                                      T                          44                                                                                                                                          ]                    ⁡                      [                                                                                b                    3                                                                                                                                                                                            b                          4                                                                                                                                                              a                          3                                                                                                                                                              a                          4                                                                                                                                          ]                                              (                  Equation          ⁢                      xe2x80x83                    ⁢          5          ⁢          B                )            
The four-port network of FIG. 4 may be a balanced circuit. A balanced circuit, as defined herein, is a circuit that includes a pair of ports that are driven as a pair, with neither port of the pair being connected to ground. Examples of balanced circuits are circuits that have differential or common mode inputs. A balanced circuit need not be completely symmetrical. Balanced circuits have often been used in the pursuit of lower power consumption, smaller size, better electromagnetic interference (EMI) behavior and lower cost. This is especially true for consumer electronics. The behavior of the class of balanced devices are illustrated in FIGS. 5A-5D. In these FIGS., a four-port device 502 is treated as two pairs of ports (i.e., ports 1 and 2 making up one pair, and ports 3 and 4 making up another pair), where each pair may be driven either differentially or common mode. The outputs can also be measured in a differential or common-mode sense. FIG. 5A illustrates a common-mode (i.e., in-phase) input and a common mode output. FIG. 5B illustrates a common mode input and a differential (i.e., 180 degrees out of phase) output. FIG. 5C illustrates a differential input and a common mode output. FIG. 5D illustrates a differential input and a differential output. Additional details for embedding and/or de-embedding four-port networks are disclosed in the above incorporated patent application.
The next obstacle/question is how to handle cascaded symmetric networks, such as one including a three-port network with one single-ended port and a balanced port pair as shown in FIG. 6. The desire here is to embed or de-embed a four-port network 604 into/from a balanced side of a three-port DUT 602.
Embodiments of the present invention are directed to methods for embedding a network having an even number of ports into a device under test (DUT) having an odd number of ports. A circulator is embedded into the DUT to thereby generate an artificial device having an even number of ports. The network is then embedded into the artificial device to thereby generate a composite device. Finally, the circulator is de-embedded from the composite device to thereby generate a further composite device that is equivalent to the network embedded into the DUT. The above mentioned circulator need not be an actual circulator, but rather, can be a virtual circulator.
Embodiments of the present invention are also directed to methods for de-embedding a network having an even number of ports from a DUT having an odd number of ports. A circulator (e.g., a virtual circulator) is embedded into the DUT to thereby generate an artificial device having an even number of ports. The network is then de-embedded from the artificial device to thereby generate a composite device. Finally, the circulator is de-embedded from the composite device to thereby generate a further composite device that is equivalent to the network de-embedded from the DUT.
A specific embodiment of the present invention is directed to a method for embedding a four-port network into a three-port DUT. For example, this embodiment can be used to embed the four-port network into a balanced side of the three-port DUT. A circulator (e.g., a virtual circulator) is embedded into the three-port DUT to thereby generate an artificial four-port device. The artificial four-port device enables the use of four-port embedding techniques. The four-port network is then embedded into the artificial four-port device to thereby generate a composite four-port device. The circulator is then de-embedded from the composite four-port device. The result is a composite three-port device that is equivalent to the four-port network embedded into the three-port DUT.
Another embodiment of the present invention is directed to a method for de-embedding a four-port network from a three-port DUT. For example, this embodiment can be used to de-embed the four-port network from a balanced side of the three-port DUT. A circulator (e.g., virtual circulator) is embedded into the three-port DUT to thereby generate an artificial four-port device. The artificial four-port device enables the use of four-port de-embedding techniques. The four-port network is then de-embedded from the artificial four-port device to thereby generate a composite four-port device. The circulator is then de-embedded from the composite four-port device. The result is a composite three-port device that is equivalent to the four-port network de-embedded from the three-port DUT.